The book systematically introduces EDA technology and Verilog HDL. It well combines the basic knowledge， programming skills and practical methods of EDA technology and Verilog HDL with the actual engineering development technologies. According to the regulations and requirements of the classroom teaching and experimental operation in universities and colleges， and with the aim of enhancing the practical engineering design ability and independent innovation capability of students， the authors reasonably arrange the content of the whole book. The book is divided into seven parts： overview of EDA technology， syntax knowledge and practical technology of Verilog HDL， detailed usage of Quartus and IP module， design technology of finite state machine， 16/32-bit practical CPU design technology and innovative practical project， Model Sim-based Test Bench simulation technology and a large number of practical system design examples. Apart from a few chapters and sections， most of the chapters arrange the corresponding exercises and a large number of highly targeted experiments and design projects. All of the Verilog HDL examples enumerated in the book have passed through the compiling or hardware testing.
The book can be used as the textbook or reference book for the subjects of electronics， computer， and automation， and can provide teaching PPT courseware， experimental source programs and demonstration videos and so on.

Chapter 1 Introduction
1.1 EDA Technology
1.2 Object for EDA Technology
1.3 Common Hardware Description Languages
1.4 Advantages of EDA Technology
1.5 Development Flow for FPGA and CPLD
1.5.1 Design Input
1.5.2 Synthesis
1.5.3 Fit (Place and Route)
1.5.4 Simulation
1.5.5 RTL Description
1.6 Programmable Logic Devices
1.6.1 Classification of PLD
1.6.2 Programming Principle of PROM
1.6.3 GAL
1.7 Structure and Programming Principle of CPLD
1.8 Structure and Working Principle of FPGA
1.8.1 Logical Structure of LUT
1.8.2 Structural Principle of Cyclone 4E Series Devices
1.8.3 FPGA Device with Embedded Flash
1.8.4 Major Manufacturers of FPGA
1.9 Hardware Testing Technology
1.9.1 Internal Logic Test
1.9.2 JTAG Boundary Scan Test
1.10 Programming and Configuration
1.11 Quartus
1.12 IP Core
1.13 Major EDA Software Companies
1.14 Development Trend of EDA
Exercises
Chapter 2 Program Structure and Data Type
2.1 Verilog Program Structure
2.1.1 Expression of Verilog Module
2.1.2 Signal Name and Mode of Verilog Module Port
2.1.3 Definition of Verilog Signal Type
2.1.4 Function Description of Verilog Module
2.2 Data Types of Verilog
2.2.1 Net Type
2.2.2 Definition of Wire Type Variable
2.2.3 Register Type
2.2.4 Definition of Register Type Variable
2.2.5 Definition of Integer Type Variable
2.2.6 Memory Type
2.3 Verilog Syntax Rules
2.3.1 Four Logical States in Verilog
2.3.2 Digital Expression Forms of Verilog
2.3.3 Expression of Data Type
2.3.4 Constant
2.3.5 Identifiers, Keywords, and Other Syntax Rules
2.3.6 Usage of parameter and localparam
Exercises
Chapter 3 Behavioral Statements
3.1 Procedural Statement
3.1.1 always Statement
3.1.2 The Application of always Statement in D flip-flop Design
3.1.3 The Application of Multi-Process and Asynchronous Sequential Circuit Design
3.1.4 Verilog Expression of Simple Up Counter
3.1.5 initial Statement
3.2 Block Statement
3.3 case Conditional Statement
3.4 if Conditional Statement
3.4.1 General Expression of if Statement
3.4.2 Combinational Circuit Design Based on if Statement
3.4.3 Sequential Circuit Design Based on if Statement
3.4.4 Design of DFF with Asynchronous Reset and Clock Enable
3.4.5 Design of DFF with Synchronous Reset
3.4.6 Design of Latches with Clear
3.4.7 Characteristics and Rules of Clock Procedural Statement
3.4.8 Practical Up Counter Design
3.4.9 Shift Register Design with Synchronized Preset Function
3.4.10 Conditional Instructions in if Statements
3.5 Statement of Procedural Assignment
3.6 Loop Statement
3.6.1 for Statement
3.6.2 while Statement
3.6.3 repeat Statement
3.6.4 forever Statement
3.7 task and function Statements
Exercises
Chapter 4 FPGA Hardware Implementation
4.1 Code Editing Input and System Compilation
4.1.1 Design File Edit and Input
4.1.2 Creating a Project
4.1.3 Constraint Item Setting
4.1.4 Comprehensive Synthesis and Compilation
4.1.5 Application of RTL Viewer
4.2 Timing Simulation
4.3 Hardware Testing
4.3.1 Pin Assignment
4.3.2 Compiled File Download
4.3.3 Indirect Programming of Configuration Chip through JTAG
4.3.4 USB-Blaster Driver Installation
4.4 Circuit Schematic Design Flow
4.4.1 Half-adder Design
4.4.2 Top-level Design of Full-adder
4.4.3 Timing Simulation and Hardware Testing of Full Adders
4.5 Pin Assignment Using Attributes
4.6 Usage of SignalTap II
4.7 Trigger Signal Edit of SignalTap II
4.8 Installation of Quartus II 13.
Exercises
Labs and Designs
Lab 4-1 Multiplexer Design
Lab 4-2 Hexadecimal 7-segment Digital Display Decoder Design
Lab 4-3 8-bit Hardware Multiplier Design
Lab 4-4 Design of a Digital Frequency Meter Using Macro Modules
Lab 4-5 Counter Design
Lab 4-6 Digital Scan and Display Circuit Design
Lab 4-7 Half-integer and Odd Frequency Divider Design
Chapter 5 Operators and Structural Description Statement
5.1 Operators of Operation
5.1.1 Bit Logical Operator
5.1.2 Logical Operator
5.1.3 Arithmetical Operator
5.1.4 Relational Operator
5.1.5 Example of Adder based on BCD Code
5.1.6 Contraction Operator
5.1.7 Parallel Connection Operator
5.1.8 Shift Operator
5.1.9 Example of Shift Operator
5.1.10 Conditional Operator
5.2 Continuous Assignment Statement
5.3 Instantiation Statement
5.3.1 Half-adder Design
5.3.2 Full-adder Design
5.3.3 Verilog Instantiation Statement and Its Usage
5.4 Application of Parameter Transmission Statement
5.5 Structural Description with Library Component
5.6 Compiling Directive Statement
5.6.1 Macro Definition Statement
5.6.2 File Inclusive Statement, 'include
5.6.3 Conditional Compilation Statement, 'ifdef, 'else, 'endif
5.7 Application of Attribute of Keep
5.8 Usage of SingalProbe
Exercises
Labs and Designs
Lab 5-1 High-speed Hardware Divider Design
Lab 5-2 Design of Various Types of Shift Registers
Lab 5-3 Verilog Code-based Frequency Meter Design
Lab 5-4 8-bit Adder Design
Lab 5-5 VGA Displayer Control Circuit Design
Chapter 6 The Usage of LPM Macro Module
6.1 The Example of Invoking Macro Module of Counter
6.1.1 The Invoking of the Text Code of the Counter LPM Module
6.1.2 Application of LPM Counter Code and Parameter Transmission Statement
6.1.3 Project Creation and Simulation Testing
6.2 Example of Building Attribute Control Multiplier
6.3 Usage of Macro Block of LPM_RAM
6.3.1 Initialization File and Its Generation
6.3.2 Invoking LPM_RAM by Schematic Diagram Method
6.3.3 Test LPM_RAM
6.3.4 Expression of Memory Initialization File Loading of Verilog Code Description
6.3.5 Structure Control of Memory Design
6.4 Usage Examples of LPM_ROM
6.4.1 Design of Simple Sinusoidal Signal Generator
6.4.2 Hardware Implementation and Testing of Sinusoidal Signal Generator
6.5 Application of In-System Memory Content Editor
6.6 Invoke of Embedded PLL of LPM
6.6.1 Building Embedded PLL Component
6.6.2 PLL Test
6.7 The Usage of In-System Sources and Probes Editor
6.8 Principle and Application of DDS
6.8.1 Principle of DDS
6.8.2 Example of DDS Signal Generator
Exercises
Labs and Designs
Lab 6-1 Look-up Table based Hardware Operator Design
Lab 6-2 Sinusoidal Signal Generator Design
Lab 6-3 Design of Simple Data Acquisition System
Lab 6-4 DDS-based Sinusoidal Signal Generator Design
Lab 6-5 Phase-shifted Signal Generator Design
Lab 6-6 Amplitude-Modulated Signal Generator Design
Lab 6-7 Hardware-Based De-jitter Circuit Design
Chapter 7 Deep Understanding of Verilog HDL
7.1 Two Types of Assignment Statements in Process
7.1.1 Blocking Assignment with Unspecified Time-delay
7.1.2 Blocking Assignment with Specified Time-delay
7.1.3 Non-blocking Assignment with Unspecified Time-delay
7.1.4 Non-blocking Assignment with Specified Time-delay
7.1.5 Deep Understanding of the Features of Blocking and Non-blocking Assignments
7.1.6 Further Discussion of Different Initialization Ways
7.2 Discussion of Procedural Statement
7.2.1 Conclusion of Procedural Statement Application
7.2.2 Relationship between Incomplete Conditional Statement and Sequential Circuit
7.3 Design of Three-state and Bidirectional Port
7.3.1 Design of Three-state Control Circuit
7.3.2 Design of Bidirectional Port
7.3.3 Design of Three-state Bus Control Circuit
7.4 Resource Optimization
7.4.1 Resource Sharing
7.4.2 Logic Optimization
7.4.3 Serialization
7.5 Speed Optimization
Exercises
Labs and Designs
Lab 7-1 Design of the Signal Detection Circuit of 4×4 Array Keyboard
Lab 7-2 Design of Direct Current Motor-based Synthesized Measurement and Control System
Lab 7-3 Design of Control Module of VGA-based Simple Image Displaying
Lab 7-4 Design of Hardware-based Music Performing Circuit
Lab 7-5 Design of Electronic Organ Circuit based on PS2 Keyboard Control Model
Chapter 8 Design Technology of State Machine
8.1 General Form of Verilog State Machine
8.1.1 Characteristics and Advantages of State Machine
8.1.2 General Structure of State Machine
8.1.3 Initial Control and Expression
8.2 Moore-type State Machine
8.2.1 State Machine with Multiprocess Structure
8.2.2 Sequence Detector and Its State Machine Design
8.3 Mealy-type State Machine
8.4 State Machine with Different Coding Types
8.4.1 Direct Output Coding
8.4.2 Defining the State Coding with the Use of Macro Definition Statement
8.4.3 Sequential Coding
8.4.4 One-hot Coding
8.4.5 Setting of State Coding
8.5 Design of Safe State Machine
8.5.1 State Guiding Method
8.5.2 Monitoring Method of State Coding
8.5.3 Auto-generation of Safe State Machine with the Use of EDA Tool
Exercises
Labs and Designs
Lab 8-1 Design of Sequence Detector
Lab 8-2 Design of ADC Sampling Control Circuit
Lab 8-3 Design of Intelligent and Logical Pen with Five Functions
Lab 8-4 Design of Data Acquisition Module
Chapter 9 16/32-bit CPU Innovation Design
9.1 Architecture and Characteristics of KX
9.2 Design of KX9016 Basic Hardware System
9.2.1 Module of One-step Beat Generation
9.2.2 ALU Module
9.2.3 Comparator Module
9.2.4 Basic Register and Register Array
9.2.5 Shifting Register Module
9.2.6 Program and Data Memory Module
9.3 Design of KX9016v1 Instruction System
9.3.1 Instruction Format
9.3.2 Instruction Operation Code
9.3.3 Example of Software Program Design
9.3.4 Design of KX9016 Controller
9.3.5 Example of Instruction Design
9.4 Timing Simulation and Hardware Testing of KX
9.4.1 Timing Simulation and Waveform Analysis of Instruction Execution
9.4.2 Hardware Testing of CPU Operation Condition
9.5 Examples of Application Program Design and System Optimization of KX
9.5.1 Multiplication Algorithm and Its Hardware Implementation
9.5.2 Division Algorithm and Its Hardware Implementation
9.5.3 Optimization of KX9016v1 Hardware System
9.6 Design of 32-bit RISC-V Processor
9.6.1 RISC-V Basic Structure and Basic Integer Instruction Set RV32I
9.6.2 2-bit Multiplication Instruction Set RV32M
9.6.3 16-bit Compressed Instruction Set RVC
Exercises
Labs and Designs
Lab 9-1 Comprehensive Experiment of 16-bit CPU Design
Lab 9-2 Experiment of New Instruction Design and Program Testing
Lab 9-3 Optimization Design and Innovation of 16-bit CPU
Chapter 10 Verilog HDL Simulation
10.1 Verilog HDL Simulation Flow
10.2 Example of Verilog Test Bench
10.3 Testing Flow of Verilog Test Bench
10.4 Verilog System Tasks and System Functions
10.4.1 System Tasks and System Functions
10.4.2 Precompiled Statements
10.5 Delay Model
10.5.1 # Delay and Gate Delay
10.5.2 Delay Description Block
10.6 Other Simulation Statements
10.6.1 fork-join Block Statements
10.6.2 wait Statement
10.6.3 force, release Statement
10.6.4 deassign Statement
10.7 Generation of Simulation Excitation Signals
10.8 Digital System Simulation
Exercises
Labs and Designs
Lab 10-1 Simulating the Test Bench of Counter on ModelSim
Lab 10-2 Design and Simulate a 16-Bit accumulator on ModelSim
Appendix A Development Systems and Softwares for EDA
A.1 KX-CDS Series EDA/SOPC System
A.1.1 Modular Independent Innovation Experimental Design Structure
A.1.2 Multifunctional Reconfigurable High-Efficiency Experimental Control System
A.1.3 FPGA Core Board of Different Functional Types
A.2 Some Expansion Modules for Experiments
A.3 Usage of MIF file generator
A.4 Reference Table for Extending Core Board FPGA to KX-CDS System
A.5 Part of the Experimental Circuit Diagram with Switchable Multifunctional Reconfigurable Structure
A.6 HX1006A and Pin Assignment Tool
References