本书由2017年图灵奖得主Patterson和Hennessy共同撰写，是计算机体系结构领域的经典书籍，强调软硬件协同设计及其对性能的影响。本书采用开源的RISC-V指令系统体系结构，讲解硬件技术、指令、算术运算、流水线、存储层次、I/O以及并行处理器等。第2版将RV64切换为RV32以降低学习难度，新增关于领域定制体系结构（DSA）的讨论以反映新的技术趋势。此外，每一章都增加了“性能提升”和“自学”章节，并更新了大量练习题。本书适合计算机体系结构领域的专业技术人员参考，也适合高等院校计算机相关专业的学生阅读。

戴维·A.帕特森（David A.Patterson），Patterson与Hennessy共同荣获了2017年度“图灵奖”，以表彰他们在计算机体系结构领域的开创性贡献。Patterson现为Google杰出工程师，之前为加州大学伯克利分校教授。他曾任ACM主席一职，目前是ACM和IEEE会士，美国艺术与科学院和计算机历史博物馆院士，并入选了美国国家工程院、国家科学院和硅谷工程名人堂。他领导了RISC I的设计与实现工作，并且是RAID项目的领导者。

1 Computer Abstractions and Technology
1.1 Introduction
1.2 Seven Great Ideas in Computer Architecture
1.3 Below Your Program
1.4 Under the Covers
1.5 Technologies for Building Processors and Memory
1.6 Performance
1.7 The Power Wall
1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
1.9 Real Stuff: Benchmarking the Intel Core i
1.10 Going Faster: Matrix Multiply in Python
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspective and Further Reading
1.14 Self-Study
1.15 Exercises
2 Instructions: Language of the Computer
2.1 Introduction
2.2 Operations of the Computer Hardware
2.3 Operands of the Computer Hardware
2.4 Signed and Unsigned Numbers
2.5 Representing Instructions in the Computer
2.6 Logical Operations
2.7 Instructions for Making Decisions
2.8 Supporting Procedures in Computer Hardware
2.9 Communicating with People
2.10 RISC-V Addressing for Wide Immediates and Addresses
2.11 Parallelism and Instructions: Synchronization
2.12 Translating and Starting a Program
2.13 A C Sort Example to Put it All Together
2.14 Arrays versus Pointers
2.15 Advanced Material: Compiling C and Interpreting Java
2.16 Real Stuff: MIPS Instructions
2.17 Real Stuff: ARMv7 (32-bit) Instructions
2.18 Real Stuff: ARMv8 (64-bit) Instructions
2.19 Real Stuff: x86 Instructions
2.20 Real Stuff: The Rest of the RISC-V Instruction Set
2.21 Going Faster: Matrix Multiply in C
2.22 Fallacies and Pitfalls
2.23 Concluding Remarks
2.24 Historical Perspective and Further Reading
2.25 Self-Study
2.26 Exercises
3 Arithmetic for Computers
3.1 Introduction
3.2 Addition and Subtraction
3.3 Multiplication
3.4 Division
3.5 Floating Point
3.6 Parallelism and Computer Arithmetic: Subword Parallelism
3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x
3.8 Going Faster: Subword Parallelism and Matrix Multiply
3.9 Fallacies and Pitfalls
3.10 Concluding Remarks
3.11 Historical Perspective and Further Reading
3.12 Self-Study
3.13 Exercises
4 The Processor
4.1 Introduction
4.2 Logic Design Conventions
4.3 Building a Datapath
4.4 A Simple Implementation Scheme
4.5 Multicycle Implementation
4.6 An Overview of Pipelining
4.7 Pipelined Datapath and Control
4.8 Data Hazards: Forwarding versus Stalling
4.9 Control Hazards
4.10 Exceptions
4.11 Parallelism via Instructions
4.12 Putting It All Together: The Intel Core i7 6700 and ARM Cortex
4.13 Going Faster: Instruction-Level Parallelism and Matrix Multiply
4.14 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and
More Pipelining Illustrations
4.15 Fallacies and Pitfalls
4.16 Concluding Remarks
4.17 Historical Perspective and Further Reading
4.18 Self-Study
4.19 Exercises
5 Large and Fast: Exploiting Memory Hierarchy
5.1 Introduction
5.2 Memory Technologies
5.3 The Basics of Caches
5.4 Measuring and Improving Cache Performance
5.5 Dependable Memory Hierarchy
5.6 Virtual Machines
5.7 Virtual Memory
5.8 A Common Framework for Memory Hierarchy
5.9 Using a Finite-State Machine to Control a Simple Cache
5.10 Parallelism and Memory Hierarchy: Cache Coherence
5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
5.12 Advanced Material: Implementing Cache Controllers
5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies
5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions
5.15 Going Faster: Cache Blocking and Matrix Multiply
5.16 Fallacies and Pitfalls
5.17 Concluding Remarks
5.18 Historical Perspective and Further Reading
5.19 Self-Study
5.20 Exercises
6 Parallel Process