本书是近年来惟一一本专门讨论时序及时序验证的专著。

本书前两章侧重于介绍时序及时序验证的概念与方法。它首先通过对比功能仿真、动态时序仿真与静态时序验证，指出静态时序验证是唯一快速有效并全面验证芯片是否满足其时序规约的手段；通过电路图和表格方式细致地介绍了时序方面的各种基础概念，如路径延迟、传播延迟、相位偏差、关键路径；解释了内在延迟和外在延迟的各种成因；并以i960处理器的EDRAM接口时序图为例讲述了接口时序分析方法。

本书继而详细地阐述了时钟和时序规约、时序验证的各种概念；讨论了各种时钟方案，如门控时钟、时钟网络/时钟分布结构、多频率时钟和多相位时钟等；细致地讨论了静态时序分析中可以采用的各种手段，如设置无效路径、多周期路径、施加各方面时序约束。

本书后两章分别针对专用集成电路(ASIC)和基于可编程逻辑器件的设计展开时序方面的讨论。

本书是近10年来惟一一本专门讨论时序及时序验证的专著，共分4章。本书全面讨论了静态时序验证的各方面内容；全书不仅紧密结合电路图和波形图进行讲解，还结合Synopsys公司的逻辑综合和静态时序分析工具讲解如何通过命令加以实现；介绍过程中不仅从理论上阐述了延迟模型，而且注重实践环节，引入了大量实际示例加以深入探讨。这种写作风格将促进读者能够更全面、细致地理解所讲内容，因此本书十分适合自学。

List of Figures

List of Tables

Preface

Acknowledgments

1 Introduction to Timing Verification

 1.1 Introduction

 1.2 Overview of Timing Verification

1.2.1 Intrinsic vs. Extrinsic Delay

1.2.2 Path Delay

 1.3 Interface Timing Analysis

2 Elements of Timing Verification

 2.1 Introduction

 2.2 Clock Definitions

2.2.1 Gated Clocks

2.2.2 Clock Skews and Multiple Clock Groups

2.2.3 Multifrequency Clocks

2.2.4 Multiphase Clocks

 2.3 More on STA

2.3.1 False Paths

2.3.2 Multicycle Path Analysis

2.3.3 Timing Specifications

2.3.4 Timing Checks

 2.4 Timing Analysis of Phase-Locked Loops

2.4.1 PLL Basics

2.4.2 PLL Ideal Behavior

2.4.3 PLL Errors

3 Timing in ASICs

 3.2 Prelayout Timing

3.2.1 RTL vs. Gate-Level Timing

3.2.2 Timing in RTL Code

3.2.3 Delay with a Continuous Assignment Statement

3.2.4 Delay in a Process Statement

3.2.5 Intra-Assignment Delays

3.2.6 The Verilog Specify Block

3.2.7 Timing in-Gate Level Code

3.2.8 Synthesis and Timing Constraints

3.2.9 Design Rule Constraints

3.2.10 Optimization Constraints

3.2.11 Gate and Wire-Load Models

3.2.12 The Synthesis Flow

3.2.13 Synthesis Tips

3.2.14 Back Annotation to Gate-Level RTL

 3.3 Postlavout Timing

3.3.1 Manual Line-Propagation Delay Calculations

3.3.2 Signal-Line Capacitance Calculation

3.3.3 Signal Line Resistance Calculation

3.3.4 Signal Trace RC Delay Evaluation

 3.4 ASIC Sign-Off Checklist

3.4.1 Library Development

3.4.2 Functional Specification

3.4.3 RTL Coding

3.4.4 Simulations of RTL

3.4.5 Logic Synthesis

3.4.6 Test Insertion and ATPG

3.4.7 Postsynthesis Gate-Level Simulation or Static Timing Analysis

3.4.8 Floorplanning

3.4.9 Place and Route

3.4.10 Final Verification of the Extracted Netlist

3.4.11 Mask Generation and Fabrication

3.4.12 Testing

4 Programmable Logic Based Design

4.1 Introduction

4.2 Programmable Logic Structures

  4.2.1 Logic Block

  4.2.2 Input/Output Block

  4.2.3 Routing Facilities

 4.3 Design Flow

 4.4 Timing Parameters

4.4.1 Timing Derating Factors

4.4.2 Grading ProgrAmmable Logic Devices by Speed

4.4.3 Best-Case Delay Values

 4.5 Timing Analysis

4.5.1 Actel ACT FPGA FAmily

4.5.2 Actel ACT 3 Architecture

4.5.3 Actel ACT 3 Timing Model

4.5.4 Altera FLEX 8000

4.5.5 Altera FLEX 8000 Architecture

4.5.6 Altera FLEX 8000 Timing Model

4.5.7 Xilinx XC3000/XC4000 FPGA Families

4.5.8 Xiilnx XC9500 CPLD

4.5.9 Xilinx XC9500 CPLD Architecture

4.5.10 Xilinx XC9500 CPLD Timing Model

 4.6 HDL Synthesis

 4.7 Software Development Systems

4.7.1 Timing Constraints

4.7.2 Operating Conditions

4.7.3 Static Timing Analysis

4.7.4 Vendor-Specific Timing-Verification Tools

4.7.5 Actel Designer

4.7.6 Altera MAX+PLUS II

4.7.7 Xilinx XACT/M1

A PrimeTime

B Pearl

C TimingDesigner

D Transistor-Level Timing Verification

 References

 Index

 About the Author