《模拟CMOS集成电路设计(英文版)》涵盖模拟CMOS集成电路分析、设计的完整流程，是学习模拟电路设计的入门宝典。将电路的基本概念、设计原理与实际工程应用关联，理论与实际结合，激发读者的兴趣。在阐述各种模拟电路的改进和新电路结构的产生时，着重观察和分析，不断地提出问题和解决问题。

通过学习本书对电路的严谨分析，逐步掌握用CMOS工艺技术来设计模拟电路。本书由Behzad Razavi(拉扎维)著。

《模拟CMOS集成电路设计(英文版)》介绍模拟CMOS集成电路的分析与设计，着重讲解技术的最新进展和设计实例，从MOSFET器件的基本物理特性开始，逐章分析CMOS放大单元电路、差分放大器、频率响应、噪声、反馈放大器与稳定性、运算放大器、电压基准源与电流基准源、离散时间系统、差分电路及反馈系统中的非线性、振荡器和锁相环等基础模拟电路的分析与设计。

《模拟CMOS集成电路设计(英文版)》还介绍了集成电路的基本制造工艺、版图和封装设计的基本原则。本书自出版以来得到了国内外读者的好评和青睐，被许多国际知名大学选为教科书。同时，由于原著者在世界知名顶级公司的丰富研究经历，使本书也非常适合作为CMOS模拟集成电路设计或相关领域的研究人员和工程技术人员的参考书。本书由Behzad Razavi(拉扎维)著。

About the Author

Preface

Acknowledgments

1 Introduction to Analog Design

 1.1 Why Analog?

 1.2 Why Integrated?

 1.3 Why CMOS?

 1.4 Why This Book?

 1.5 General Concepts

1.5.1 Levels of Abstraction

1.5.2 Robust Analog Design

2 Basic MOS Device Physics

 2.1 General Considerations

2.1.1 MOSFET as a Switch

2.1.2 MOSFET Structure

2.1.3 MOS Symbols

 2.2 MOS I/V Characteristics

2.2.1 Threshold Voltage

2.2.2 Derivation of I/V Characteristics

 2.3 Second-Order Effects

 2.4 MOS Device Models

2.4.1 MOS Device Layout

2.4.2 MOS Device Capacitances

2.4.3 MOS Small-Signal Model

2.4.4 MOS SPICE models

2.4.5 NMOS versus PMOS Devices

2.4.6 Long-Channel versus Short-Channel Devices

3 Single-Stage Amplifiers

 3.1 Basic Concepts

 3.2 Common-Source Stage

3.2.1 Common-Source Stage with Resistive Load

3.2.2 CS Stage with Diode-Connected Load

3.2.3 CS Stage with Current-Source Load

3.2.4 CS Stage with Triode Load

3.2.5 CS Stage with Source Degeneration

 3.3 Source Follower

 3.4 Common-Gate Stage

 3.5 Cascode Stage

3.5.1 Folded Cascode

 3.6 Choice of Device Models

4 Differential Amplifiers

 4.1 Single-Ended and Differential Operation

 4.2 Basic Differential Pair

4.2.1 Qualitative Analysis

4.2.2 Quantitative Analysis

 4.3 Common-Mode Response

 4.4 Differential Pair with MOS Loads

 4.5 Gilbert Cell

5 Passive and Active Current Mirrors

 5.1 Basic Current Mirrors

 5.2 Cascode Current Mirrors

 5.3 Active Current Mirrors

5.3.1 Large-Signal Analysis

5.3.2 Small-Signal Analysis

5.3.3 Common-Mode Properties

5 Frequency Response of Amplifiers

 6.1 General Considerations

6.1.1 Miller Effect

6.1.2 Association of Poles with Nodes

 6.2 Common-Source Stage

 6.3 Source Followers

 6.4 Common-Gate Stage

 6.5 Cascode Stage

 6.6 Differential Pair

 Appendix A: Dual of Miller's Theorem

7 Noise

 7.1 Statistical Characteristics of Noise

 7.1.1 Noise Spectrum

7.1.2 Amplitude Distribution

7.1.3 Correlated and Uncorrelated Sources

 7.2 Types of Noise

7.2.1 Thermal Noise

7.2.2 Flicker Noise

 7.3 Representation of Noise in Circuits

 7.4 Noise in Single-Stage Amplifiers

7.4.1 Common-Source Stage

7.4.2 Common-Gate Stage

7.4.3 Source Followers

7.4.4 Cascode Stage

 7.5 Noise in Differential Pairs

 7.6 Noise Bandwidth

8 Feedback

 8.1 General Considerations

8.1.1 Properties of Feedback Circuits

8.1.2 Types of Amplifiers

 8.2 Feedback Topologies

8.2.1 Voltage-Voltage Feedback

8.2.2 Current-Voltage Feedback

8.2.3 Voltage-Current Feedback

8.2.4 Current-Current Feedback

 8.3 Effect of Loading

8.3.1 Two-Port Network Models

8.3.2 Loading in Voltage-Voltage Feedback

8.3.3 Loading in Current-Voltage Feedback

8.3.4 Loading in Voltage-Current Feedback

8.3.5 Loading in Current-Current Feedback

8.3.6 Summary of Loading Effects

 8.4 Effect of Feedback on Noise

9 Operational Amplifiers

 9.1 General Considerations

9.1.1 Performance Parameters

 9.2 One-Stage Op Amps

 9.3 Two-Stage Op Amps

 9.4 Gain Boosting

 9.5 Comparison

 9.6 Common-Mode Feedback

 9.7 Input Range Limitations

 9.8 Slew Rate

 9.9 Power Supply Rejection

 9.10 Noise in 0p Amps

10 Stability and Frequency Compensation

 10.1 General Considerations

 10.2 Multipole Systems

 10.3 Phase Margin

 10.4 Frequency Compensation

 10.5 Compensation of Two-Stage Op Amps

10.5.1 Slewing in Two-Stage Op Amps

 10.6 Other Compensation Techniques

11 Bandgap References

 11.1 General Considerations

 11.2 Supply-Independent Biasing

 11.3 Temperature-Independent References

11.3.1 Negative-TC Voltage

11.3.2 Positive-TC Voltage

11.3.3 Bandgap Reference

 11A PTAT Current Generation

 11.5 Constant-Gin Biasing

 11.6 Speed and Noise Issues

 11.7 Case Study

12 Introduction to Switched-Capacitor Circuits

 12.1 General Considerations

 12.2 Sampling Switches

12.2.1 MOSFETS as Switches

12.2.2 Speed Considerations

12.2.3 Precision Considerations

12.2.4 Charge Injection Cancellation

 12.3 Switched-Capacitor Amplifiers

12.3.1 Unity-Gain S ampler/Buffer

12.3.2 Noninverting Amplifier

12.3.3 Precision Multiply-by-Two Circuit

 12.4 Switched-Capacitor Integrator

 12.5 Switched-Capacitor Common-Mode Feedback

13 Nonlinearity and Mismatch

 13.1 Nonlinearity

13.1.1 General Considerations

13.1.2 Nonlinearity of Differential Circuits

13.1.3 Effect of Negative Feedback on Nonlinearity

13.1.4 Capacitor Nonlinearity

13.1.5 Linearization Techniques

 13.2 Mismatch

13.2.1 Offset Cancellation Techniques

13.2.2 Reduction of Noise by Offset Cancellation

13.2.3 Alternative Definition of CMRR

14 Oscillators

 14.1 General Considerations

 14.2 Ring Oscillators

 14.3 LC Oscillators

14.3.1 Crossed-Coupled Oscillator

14.3.2 Colpitts Oscillator

14.3.3 One-Port Oscillators

 14.4 Voltage-Controlled Oscillators

14.4.1 Tuning in Ring Oscillators

14.4.2 Tuning in LC Oscillators

 14.5 Mathematical Model of VCOs

15 Phase-Locked Loops

 15.1 Simple PLL

15.1.1 Phase Detector

15.1.2 Basic PLL Topology

15.1.3 Dynamics of Simple PLL

 15.2 Charge-Pump PLLs

15.2.1 Problem of Lock Acquisition

15.2.2 Phase/Frequency Detector and Charge Pump

15.2.3 Basic Charge-Pump PLL

 15.3 Nonideal Effects in PLLs

15.3.1 PFD/CP Nonidealities

15.3.2 Jitter in PLLs

 15.4 Delay-Locked Loops

 15.5 Applications

15.5.1 Frequency Multiplication and Synthesis

15.5.2 Skew Reduction

15.5.3 Jitter Reduction

16 Short-Channel Effects and Device Models

 16.1 Scaling Theory

 16.2 Short-Channel Effects

16.2.1 Threshold Voltage Variation

16.2.2 Mobility Degradation with Vertical Field

16.2.3 Velocity Saturation

16.2.4 Hot Carrier Effects

16.2.5 Output Impedance Variation with Drain-Source Voltage

 16.3 MOS Device Models

16.3.1 Level 1 Model

16.3.2 Level 2 Model

16.3.3 Level 3 Model

16.3.4 BSIM Series

16.3.5 Other Models

16.3.6 Charge and Capacitance Modeling

16.3.7 Temperature Dependence

 16.4 Process Comers

 16.5 Analog Design in a Digital World

17 CMOS Processing Technology

 17.1 General Considerations

 17.2 Wafer Processing

 17.3 Photolithography

 17.4 Oxidation

 17.5 Ion Implantation

 17.6 Deposition and Etching

 17.7 Device Fabrication

17.7.1 Active Devices

17.7.2 Passive Devices

17.7.3 Interconnects

 17.8 Latch-Up

18 Layout and Packaging

 18.1 General Layout Considerations

18.1.1 Design Rules

18.1.2 Antenna Effect

 18.2 Analog Layout Techniques

18.2.1 Multifinger Transistors

18.2.2 Symmetry

18.2.3 Reference Distribution

18.2.4 Passive Devices

18.2.5 Interconnects

 18.3 Substrate Coupling

 Index